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| ds07-12617-1e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 8-bit proprietary microcontrollers cmos f 2 mc-8fx mb95100b series mb95107b/f108bs/f108bw/r107b/d108bs/ mb95d108bw/fv100d-101 description the mb95100b series is general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. feature ? f 2 mc-8fx cpu core instruction set optimized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock sub clock (for dual clock product) sub pll clock (for dual clock product) (continued)
mb95100b series 2 (continued) ? timer 8/16-bit compound timer 2 channels 16-bit reload timer 8/16-bit ppg 2 channels 16-bit ppg 2 channels timebase timer watch prescaler (for dual clock product) ? fram 2k bytes fram is loaded (mb95r 107b/mb95d108bs/mb95d108bw only) ? lin-uart full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? uart/sio full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? i 2 c* built-in wake-up function ? external interrupt interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected. ? low-power consumption (standby) mode stop mode sleep mode watch mode (for dual clock product) timebase timer mode ? i/o port the number of maximum ports ? single clock product : 55 ports ? dual clock product : 53 ports port configuration ? general-purpose i/o ports (n-ch open drain) other than mb95d108bs/mb95d108bw/mb95r107b : 6 ports mb95d108bs/mb95d108bw/mb95r107b : 4 ports ? general-purpose i/o ports (cmos) single clock product : 49 ports dual clock product : 47 ports * : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. mb95100b series 3 product lineup (continued) part number parameter mb95107b mb95f108bs/ mb95f108bw mb95r107b* 3 mb95d108bs/ mb95d108bw type mask rom product flash memory product mask rom product flash memory product rom capacity 48k bytes 60k bytes 48k bytes 60k bytes ram capacity 2k bytes fram capacity no 2k bytes reset output no option* 4 clock system selectable single/dual clock* 1 single/dual clock* 2 selectable single/dual clock* 1 single/dual clock* 2 low voltage detection reset no cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) peripheral functions general purpose i/o ports ? single clock product : 55 ports (n-ch open drain * 5 : 4/6 ports, cmos : 49 ports) ? dual clock product : 53 ports (n-ch open drain * 5 : 4/6 ports, cmos : 47 ports) timebase timer interrupt cycle : 0.5 ms, 2.1 ms, 8. 2 ms, 32.8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : min 105 ms at sub oscillation clock 32.768 khz (for dual clock product) : min 250 ms wild register capable of r eplacing 3 bytes of rom data i 2 c master/slave sending and receiving bus error function and arbitration function detecting transmitting direction function start condition repeated generation and detection functions built-in wake-up function uart/sio data transfer capable in uart/sio full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin-uart dedicated reload timer allowing a wide ra nge of communication speeds to be set. full duplex double buffer. clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin functions available as the lin master or lin slave. 8/10-bit a/d converter (12 channels) 8-bit or 10-bit resolution can be selected. mb95100b series 4 (continued) *1 : specify clock mode when ordering mask rom. *2 : mb95f108bs/mb95d108bs is single clock and mb95f108bw/mb95d108bw is dual clock. *3 : this device is under development. *4 : for details of option, refer to ? mask option?. *5 : mb95d108bs/d108bw/r107b contain 4 general-purpose i/o ports for n-ch open dr ain. port number other than mb95d108bs/d108bw/r107b has 6 general- purpose i/o ports for n-ch open drain. *6 : embedded algorithm is a trade ma rk of advanced micro devices inc. note : part number of the evaluation products in mb 95100b series is mb95fv100d- 101. when using it, the mcu board (mb2146-301a) is required. part number parameter mb95107b mb95f108bs/ mb95f108bw mb95r107b* 3 mb95d108bs/ mb95d108bw peripheral functions 16-bit reload timer two clock modes and two counter operating m odes can be selected. square wave form output count clock : 7 internal clocks and external clock can be selected. counter operating mode : reload mode or one-shot mode can be selected. 8/16-bit compound timer (2 channels) each channel of the timer ca n be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel?. built-in timer function, pwc function, pwm function, capture function and square wave form output count clock : 7 internal clocks and external clock can be selected. 16-bit ppg (2 channels) pwm mode or one-shot mode can be selected. counter operating clock : eight selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ? 8-bit ppg 2 channels ? or ? 16-bit ppg 1 channel ? . counter operating clock : eight selectable clock sources watch counter (for dual clock product) count clock : four selectable clock s ources (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63. (cap able of counting for 1 minute when selecting clock source 1 second and se tting counter value to 60) watch prescaler (for dual clock product) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (12 channels) interrupt by edge detection (rising, fa lling, or both edges can be selected.) can be used to recover from standby modes. flash memory supports automatic progra mming, embedded algorithm tm * 6 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of write/erase cycles (minimum) : 10000 times data retention time : 20 years erase can be performed on each block boot block configuration block protection with external programming voltage flash security feature for prot ecting the content of the flash standby mode sleep, stop, watch (for dual clock product), and timebase timer mb95100b series 5 select of oscillation stabilization wait time (mask rom product only) for the mask rom product, you can set the mask option when ordering mask rom to select the initial value of main clock oscillation stabilization wait time from among the following four values. note that the evaluation and flash me mory products are fixed their initial value of main clock oscillation stabili- zation wait time at the maximum value. packages and corresponding products : available : unavailable select of oscillation stabilization wait time remarks (2 2 ? 2) /f ch 0.5 s (at main oscillation clock 4 mhz) (2 12 ? 2) /f ch approx. 1.02 ms (at main oscillation clock 4 mhz) (2 13 ? 2) /f ch approx. 2.05 ms (at main oscillation clock 4 mhz) (2 14 ? 2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) part number package mb95107b mb95r107b mb95f108bs/f108bw mb95d108bs/d108bw mb95fv100d-101 fpt-64p-m03 fpt-64p-m09 bga-224p-m08 mb95100b series 6 differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only t he functions of the mb95100b series bu t also those of other products to support software development for mu ltiple series and models of the f 2 mc-8fx family. the i/o addresses for peripheral resources not used by t he mb95100b series are therefore access -barred. read/write access to these access-barred addresses may cause per ipheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. particularly, do not use word access to odd numbered by te address in the prohibited areas (if these access are used, the address may be read or written unexpectedly). also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory and mask rom products, do not use these values in the program. the evaluation product do not support the functions of some bits in single-by te registers. read/write access to these bits does not cause hardware malfunctions. the evaluation, flash memory, and mask rom products are designed to behave completely the same way in terms of hardware and software. ? difference of memory spaces if the amount of memory on the evaluation product is di fferent from that of the flash memory or mask rom product, carefully check the differ ence in the amount of memory from the model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption the current consumption of flash memory pr oduct is greater than for mask rom product. for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage are different among the eval uation, flash memory, and mask rom products. for details of operating voltage, refer to ? electrical characteristics?. ? difference between rst and mod pins the input type of rst and mod pins is cmos input on the flash memory product. the rst and mod pins are hysteresis inputs on the mask rom pr oduct. a pull - down resistor is provided for the mod pin of the mask rom product. mb95100b series 7 pin assignment (top view) (fpt-64p-m03, fpt-64p-m09) *1 : single clock product is general-purpose port , and dual clock product is sub clock oscillation pin. *2 : p50 and p51 cannot be used in mb95r107b, mb95d108bs, and mb95d108bw. avss p30/an00 p31/an01 p32/an02 p33/an03 p34/an04 p35/an05 p36/an06 p37/an07 p40/an08 p41/an09 p42/an10 p43/an11 p67/sin p66/sot p65/sck 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avcc 148 p64/ec1 avr 247 p63/to11 pe3/int13 346 p62/to10 pe2/int12 445 p61/ppg11 pe1/int11 544 p60/ppg10 pe0/int10 643 p53/trg1 p83 742 p52/ppg1 p82 841 p51/sda0* 2 p81 940 p50/scl0* 2 p80 10 39 p24/ec0 p71/ti0 11 38 p23/to01 p70/to0 12 37 p22/to00 mod 13 36 p21/ppg01 x0 14 35 p20/ppg00 x1 15 34 p14/ppg0 vss 16 33 p13/trg0/adtg 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vcc pg0 pg2/x1a* 1 pg1/x0a* 1 rst p00/int00 p01/int01 p02/int02 p03/int03 p04/int04 p05/int05 p06/int06 p07/int07 p10/ui0 p11/uo0 p12/uck0 64 mb95100b series 8 pin description (continued) pin no. pin name i/o circuit type* function 1av cc ? a/d converter power supply pin 2 avr ? a/d converter reference input pin 3pe3/int13 p general-purpose i/o port the pins are shared with t he external interrupt input. 4pe2/int12 5pe1/int11 6pe0/int10 7p83 o general-purpose i/o port 8p82 9p81 10 p80 11 p71/ti0 h general-purpose i/o port. the pin is shared with 16 - bit reload timer ch.0 input. 12 p70/to0 general-purpose i/o port. the pin is shared with 16 - bit reload timer ch.0 output. 13 mod b an operating mode designation pin 14 x0 a main clock input oscillation pin 15 x1 main clock input/output oscillation pin 16 v ss ? power supply pin (gnd) 17 v cc ? power supply pin 18 pg0 h general-purpose i/o port. 19 pg2/x1a h/a single-system product is general-purpose port (pg2). dual-system product is sub clock input/output oscillation pin (32 khz). 20 pg1/x0a single-system product is general-purpose port (pg1). dual-system product is sub clock input oscillation pin (32 khz). 21 rst b? reset pin 22 p00/int00 c general-purpose i/o port. the pins are shared with external interrupt input. large current port. 23 p01/int01 24 p02/int02 25 p03/int03 26 p04/int04 27 p05/int05 28 p06/int06 29 p07/int07 30 p10/ui0 g general-purpose i/o port. the pin is shared with uart/sio ch.0 data input. mb95100b series 9 (continued) pin no. pin name i/o circuit type* function 31 p11/uo0 h general-purpose i/o port. the pin is shared with uart /sio ch.0 data output. 32 p12/uck0 general-purpose i/o port. the pin is shared with uart/sio ch.0 clock i/o. 33 p13/trg0/ adtg general-purpose i/o port. the pin is shared with 16-bit ppg ch .0 trigger input (trg0) and a/d converter trigger input (adtg). 34 p14/ppg0 general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 output. 35 p20/ppg00 h general-purpose i/o port. the pins are shared with 8/16-bit ppg ch.0 output. 36 p21/ppg01 37 p22/to00 general-purpose i/o port. the pins are shared with 8/16-b it compound timer ch.0 output. 38 p23/to01 39 p24/ec0 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.0 clock input. 40 p50/scl0 i general-purpose i/o port (exc ept mb95r107b , mb95d108bs, and mb95d108bw) . the pin is shared with i 2 c ch.0 clock i/o. 41 p51/sda0 general-purpose i/o port (e xcept mb95r107b, mb95d108bs, and mb95d108bw) . the pin is shared with i 2 c ch.0 data i/o. 42 p52/ppg1 h general-purpose i/o port. the pin is shared with 16-bit ppg ch.1 output. 43 p53/trg1 general-purpose i/o port. the pin is shared with 16-bit ppg ch.1 trigger input. 44 p60/ppg10 k general-purpose i/o port. the pins are shared with 8/16-bit ppg ch.1 output. 45 p61/ppg11 46 p62/to10 general-purpose i/o port. the pins are shared with 8/16-b it compound timer ch.1 output. 47 p63/to11 48 p64/ec1 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.1 clock input. 49 p65/sck general-purpose i/o port. the pin is shared with lin-uart clock i/o. 50 p66/sot general-purpose i/o port. the pin is shared with lin-uart data output. 51 p67/sin l general-purpose i/o port. the pin is shared with lin-uart data input. mb95100b series 10 (continued) * : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 52 p43/an11 j general-purpose i/o port. the pins are shared with a/ d converter analog input. 53 p42/an10 54 p41/an09 55 p40/an08 56 p37/an07 j general-purpose i/o port. the pins are shared with a/ d converter analog input. 57 p36/an06 58 p35/an05 59 p34/an04 60 p33/an03 61 p32/an02 62 p31/an01 63 p30/an00 64 av ss ? a/d converter power supply pin (gnd) mb95100b series 11 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance value : approx. 1 m ? low-speed side feedback resistance : approx. 24 m ? (evaluation product : approx. 10 m ? ) dumping resistance : approx. 144 k ? (evaluation product : without dumping resistance) b only for input hysteresis input only for mask rom product with pull-down resistor only for mask rom product b? hysteresis input only for mask rom product c cmos output hysteresis input g cmos output cmos input hysteresis input with pull-up control h cmos output hysteresis input with pull-up control x0 (x0a) x1 (x1a) n-ch standby control clock input r mode input reset input p-ch n-ch standby control external interrupt enable digital output digital output hysteresis input r p-ch n-ch p-ch pull-up control standby control digital output digital output hysteresis input cmos input p-ch n-ch r p-ch pull-up control standby control digital output digital output hysteresis input mb95100b series 12 (continued) type circuit remarks i n-ch open drain output cmos input hysteresis input p-ch transistor is existed in mb95d108bs, mb95d108bw, and mb95r107b. j cmos output hysteresis input analog input with pull-up control k cmos output hysteresis input l cmos output cmos input hysteresis input o n-ch open drain output hysteresis input n-ch p-ch standby control digital output cmos input hysteresis input r p-ch n-ch p-ch pull-up control a/d control standby control analog input digital output digital output hysteresis input p-ch n-ch standby control digital output digital output hysteresis input p-ch n-ch standby control digital output digital output hysteresis input cmos input n-ch standby control digital output hysteresis input mb95100b series 13 (continued) type circuit remarks p cmos output hysteresis input with pull-up control r p-ch n-ch p-ch standby control external interrupt control pull-up control digital outpu t digital outpu t hysteresis input mb95100b series 14 handling devices ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not exceeded when they are used. latch-up may occur on cmos ic s if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc pin and v ss pins. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc , avr) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system powe r supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the v cc power-supply voltage. for stabilization, in principle, keep the variation in v cc ripple (p-p value) in a commercial frequency range (50/60 hz) not to exceed 10 % of the standard v cc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a mome ntary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizatio n wait time is required for power-on reset, wake-up from sub clock mode or stop mode. pin connection ? treatment of unused pin leaving unused input pins unconnect ed can cause abnormal operation or latch-up, leaving to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/ output pins may be set to output mode and left open, or set to input mode and treat ed the same as unused input pins. if there is an unused output pin, make it open. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = avr = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss pins near this device. mb95100b series 15 ? mode pin (mod) connect the mod pin directly to v cc or v ss pins. to prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mod pin to v cc or v ss pin and to provide a low-impedance connection. ? analog power supply always set the same potential to av cc and v cc pins. when v cc > av cc , the current may flow through the an00 to an11 pins. ? precautions for use of fram when the device is connected to i 2 c external pins (scl0 and sda0) , the device with the same slave addresses (1010000 b to 1010111 b ) as built-in fram cannot be used. when built-in fram is used without connecting the device to i 2 c external pins, external pull-up resistor (1.1k ? or more) should be connec ted to scl0 and sda0 pins. p50 and p51 cannot be used in mb95r1 07b , mb95d108bs, and mb95d108bw. mb95100b series 16 programming flash memory microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note : for information on applicable adapter mode ls and parallel programmers, contact the following: flash support group, inc. tel: +81-53-428-8380 ? sector configuration the individual sectors of flash memory correspond to addresses used for cpu access and programming by the parallel programmer as follows: ? programming method 1) set the type code of the parallel programmer to 17226. 2) load program data to parall el programmer addresses 71000 h to 7ffff h . 3) programmed by parallel programmer package applicable adapter model parallel programmers fpt-64p-m03 tef110-108f35ap af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) af9723+af9834 (ver 02.08e or more) fpt-64p-m09 tef110-108f36ap *: programmer addresses are corresponding to cpu addresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* sa1 (4k bytes) 1000 h 71000 h 1fff h 71fff h sa2 (4k bytes) 2000 h 72000 h 2fff h 72fff h sa3 (4k bytes) 3000 h 73000 h 3fff h 73fff h sa4 (16k bytes) 4000 h 74000 h 7fff h 77fff h sa5 (16k bytes) 8000 h 78000 h bfff h 7bfff h sa6 (4k bytes) c000 h 7c000 h cfff h 7cfff h sa7 (4k bytes) d000 h 7d000 h dfff h 7dfff h sa8 (4k bytes) e000 h 7e000 h efff h 7efff h sa9 (4k bytes) f000 h 7f000 h ffff h 7ffff h lower bank upper bank mb95100b series 17 block diagram p80 to p83 p14/ppg0 p65/sck p67/sin pe0/int10 to pe3/int13 av cc av ss avr p50/scl0* 2 p51/sda0* 2 p40/an08 to p43/an11 p30/an00 to p37/an07 p21/ppg01 p22/to00 p23/to01 p24/ec0 p12/uck0 p62/to10 p61/ppg11 p60/ppg10 p63/to11 p00/int00 to p07/int07 p10/ui0 p64/ec1 p71/ti0 p66/sot p70/to0 rst x0,x1 pg2/x1a* 1 pg1/x0a* 1 pg0 mod, v cc , v ss p13/trg0/adtg p20/ppg00 p11/uo0 i 2 c f 2 mc-8fx cpu uart/sio 16-bit ppg ch.0 8/16-bit ppg ch.0 8/10-bit a/d converter c fram* 3 lin-uart 8/16-bit ppg ch.1 rom ram port port external interrupt ch.8 to ch.11 8/16-bit compound timer ch.0 16-bit reload timer 8/16-bit compound timer ch.1 interrupt control wild register reset control clock control watch prescaler watch counter external interrupt ch.0 to ch.7 internal bus p53/trg1 p52/ppg1 16-bit ppg ch.1 other pins *1 : single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. *2 : p50 and p51 cannot be used in mb 95r107b, mb95d108bs, and mb95d108bw. *3 : mb95r107b, mb95d108bs, and mb95d108bw only mb95100b series 18 cpu core 1. memory space memory space of the mb95100b series is 64 kbytes and consists of i/o area, data area, and program area. the memory space includes special-purpose areas such as the general-purpose registers and vector table. memory map of the mb95100b series is shown below. memory map 0000 h 0080 h 0100 h 0200 h 0f80 h 1000 h ffff h extended i/o ram 3.75 kbytes mb95fv100d-101 i/o 0000 h 0080 h 0100 h 0200 h 0880 h 0f80 h 1000 h ffff h flash memory 60 kbytes mb95f108bs mb95f108bw mb95d108bs mb95d108bw i/o ram 2 kbytes extended i/o 0000 h 0080 h 0100 h 0200 h 0880 h 0f80 h 1000 h 4000 h ffff h mask rom 48 kbytes mb95107b mb95r107b i/o ram 2 kbytes extended i/o register register access prohibited access prohibited access prohibited register flash memory 60 kbytes mb95100b series 19 2. register the mb95100b series has two types of registers; dedica ted registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for use as a condition code register (ccr) . (refer to the diagram below.) program counter (pc) : a 16-bit register to in dicate locations where instructions are stored accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instruction, the lower 1 byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower 1 byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer to point to a memory address stack pointer (sp) : a 16-bit register to indicate a stack area program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register pc a t ix ep sp ps : program counter 16-bit : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h ps rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dp2 dp1 dp0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status mb95100b series 20 the rp indicates the address of the register bank cu rrently being used. the relati onship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic operat ion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is cleared to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by these bits. il1 il0 interrupt level priority 00 0 high low = no interruption 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. "0" "0" "0" "0" "0" "0" "0" "1" r4 r 3 r2 r1 r0 b 2 b 1 b 0 a7 a6 a5 a4 a 3 a2 a1 a0 a15 a14 a1 3 a12 a11 a10 a9 a 8 ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower mb95100b series 21 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8- register. up to a total of 32 banks can be used on the mb95100b series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r 3 r4 r5 r6 r7 r0 r1 r2 r 3 r4 r5 r6 r7 r0 r1 r2 r 3 r4 r5 r6 r7 addre ss 100 h 107 h 1ff h 1f 8 h b a nk 3 1 b a nk 0 register bank configuration this address = 0100 h + 8 (rp) 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance. 8-bit mb95100b series 22 fram ? slave address of fram fram operates as one of the sl ave devices connected to the i 2 c, and the i 2 c is used to read from or write to fram. when data is transferred by the i 2 c, the slave address of fram is shown below. * : page select bit : set the value corresponding to the accessed page ? memory configuration of fram the capacitance of the built-in fram is 2 kbytes. the memory configuration of fr am consists of 8 pages as follows. the capacitance of each page is 256 bytes. slave address (7 bits) r/w bit (1 bit) slave id (4 bits) page select bit* (3 bits) 1010 000 b : page 0 001 b : page 1 010 b : page 2 011 b : page 3 100 b : page 4 101 b : page 5 110 b : page 6 111 b : page 7 0 : at write 1 : at read page address capacitance 000 h to ff h 256 bytes 100 h to ff h 256 bytes 200 h to ff h 256 bytes 300 h to ff h 256 bytes 400 h to ff h 256 bytes 500 h to ff h 256 bytes 600 h to ff h 256 bytes 700 h to ff h 256 bytes mb95100b series 23 notes : ? when the device is connected to i 2 c external pins (scl0 and sda0) , the device with the same addresses (1010000 b to 1010111 b ) as built-in fram cannot be used. ? when fram is used without connecting the de vice built into the pull-up resistor to i 2 c external pins, external pull-up resistor (1.1 k ? or more) should be connected to scl0 and sda0 pins. ? p50 and p51 cannot be used in mb 95r107b, mb95d108bs, and mb95d108bw. s ap a a s ap a aa msb msb msb lsb lsb lsb msb lsb msb lsb msb lsb msb lsb microcontroller microcontroller fram fram start condition start condition address & data stop condition stop condition slave address 0 slave address 0 address address data byte data byte data byte acknowledge acknowledge address & data ? single byte write ? compound byte write s a s 1p aa s 1p a 1p a as a msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb microcontroller microcontroller fram fram start condition start condition address stop condition stop condition slave address 1 slave address 1 data byte data data byte data acknowledge no acknowledge address acknowledge no acknowledge data byte acknowledge microcontroller fram start condition stop condition slave address 1 data byte data address acknowledge no acknowledge data byte acknowledge start condition address slave address 0 address ? continuous address read ? current address read ? select (random) read mb95100b series 24 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h ? (disabled) ?? 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h pdr3 port 3 data register r/w 00000000 b 0011 h ddr3 port 3 direction register r/w 00000000 b 0012 h pdr4 port 4 data register r/w 00000000 b 0013 h ddr4 port 4 direction register r/w 00000000 b 0014 h pdr5 port 5 data register r/w 00000000 b 0015 h ddr5 port 5 direction register r/w 00000000 b 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h pdr7 port 7 data register r/w 00000000 b 0019 h ddr7 port 7 direction register r/w 00000000 b 001a h pdr8 port 8 data register r/w 00000000 b 001b h ddr8 port 8 direction register r/w 00000000 b 001c h to 0025 h ? (disabled) ?? 0026 h pdre port e data register r/w 00000000 b 0027 h ddre port e direction register r/w 00000000 b 0028 h , 0029 h ? (disabled) ?? 002a h pdrg port g data register r/w 00000000 b mb95100b series 25 (continued) address register abbreviation register name r/w initial value 002b h ddrg port g direction register r/w 00000000 b 002c h ? (disabled) ?? 002d h pul1 port 1 pull - up register r/w 00000000 b 002e h pul2 port 2 pull - up register r/w 00000000 b 002f h pul3 port 3 pull - up register r/w 00000000 b 0030 h pul4 port 4 pull - up register r/w 00000000 b 0031 h pul5 port 5 pull - up register r/w 00000000 b 0032 h pul7 port 7 pull - up register r/w 00000000 b 0033 h ? (disabled) ?? 0034 h pule port e pull - up register r/w 00000000 b 0035 h pulg port g pull - up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 control status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 control status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 control status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 control status register 1 ch.1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch.1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch.1 r/w 00000000 b 003e h tmcsrh0 16-bit reload timer control status register (upper byte) ch.0 r/w 00000000 b 003f h tmcsrl0 16-bit reload timer control status register (lower byte) ch.0 r/w 00000000 b 0040 h , 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg control status r egister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg control status regi ster (lower byte) ch.0 r/w 00000000 b 0044 h pcnth1 16-bit ppg control status r egister (upper byte) ch.1 r/w 00000000 b 0045 h pcntl1 16-bit ppg control status regi ster (lower byte) ch.1 r/w 00000000 b 0046 h , 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit control register ch.0/ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch.2/ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch.6/ch.7 r/w 00000000 b 004c h eic01 external interrupt circuit control register ch.8/ch.9 r/w 00000000 b 004d h eic11 external interrupt circuit cont rol register ch.10/ch.11 r/w 00000000 b mb95100b series 26 (continued) address register abbreviation register name r/w initial value 004e h , 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicat ion control register r/w 000000xx b 0056 h smc10 uart/sio serial mode cont rol register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode c ontrol register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch.0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 005f h ? (disabled) ?? 0060 h ibcr00 i 2 c bus control register 0 ch.0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 ch.0 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register ch.0 r 00000000 b 0063 h iddr0 i 2 c data register ch.0 r/w 00000000 b 0064 h iaar0 i 2 c address register ch.0 r/w 00000000 b 0065 h iccr0 i 2 c clock control regi ster ch.0 r/w 00000000 b 0066 h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ ing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writ ing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b mb95100b series 27 (continued) address register abbreviation register name r/w initial value 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 cont rol status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 cont rol status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 cont rol status register 0 ch.1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 cont rol status register 0 ch.1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch.1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b mb95100b series 28 (continued) address register abbreviation register name r/w initial value 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch.1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch.1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch.1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch.1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h tmrh0/ tmrlrh0 16-bit timer register (upper byte) ch.0/ 16-bit reload register (upper byte) ch.0 r/w 00000000 b 0fa7 h tmrl0/ tmrlrl0 16-bit timer register (lower byte) ch.0/ 16-bit reload register (lower byte) ch.0 r/w 00000000 b 0fa8 h , 0fa9 h ? (disabled) ?? 0faa h pdcrh0 16-bit ppg down counter re gister (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter register (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer re gister (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer re gister (lower byte) ch.0 r/w 11111111 b 0fb0 h pdcrh1 16-bit ppg down counter re gister (upper byte) ch.1 r 00000000 b 0fb1 h pdcrl1 16-bit ppg down counter register (lower byte) ch.1 r 00000000 b 0fb2 h pcsrh1 16-bit ppg cycle setting buffer register (upper byte) ch.1 r/w 11111111 b 0fb3 h pcsrl1 16-bit ppg cycle setting buffer register (lower byte) ch.1 r/w 11111111 b 0fb4 h pduth1 16-bit ppg duty setting buffer register ( upper byte ) ch.1 r/w 11111111 b 0fb5 h pdutl1 16-bit ppg duty setting buffer register ( lower byte ) ch.1 r/w 11111111 b 0fb6 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate gener ator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler select register ch.0 r/w 00000000 b 0fbf h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch.0 r/w 00000000 b 0fc0 h , 0fc1 h ? (disabled) ?? 0fc2 h aidrh a/d input disable register (upper byte) r/w 00000000 b 0fc3 h aidrl a/d input disable register (lower byte) r/w 00000000 b mb95100b series 29 (continued) ? r/w access symbols ? initial value symbols note : do not write to the ? (disabled) ?. re ading the ? (disabled) ? returns an undefined value. address register abbreviation register name r/w initial value 0fc4 h to 0fe2 h ? (disabled) ?? 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ?? r/w : readable/writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. mb95100b series 30 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch.1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch.1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] 16-bit reload timer ch.0 irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] i 2 c ch.0 irq16 ffda h ffdb h l16 [1 : 0] 16-bit ppg ch.1 irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch timer/watch counter irq20 ffd2 h ffd3 h l20 [1 : 0] external interrupt ch.8 irq21 ffd0 h ffd1 h l21 [1 : 0] external interrupt ch.9 external interrupt ch.10 external interrupt ch.11 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low mb95100b series 31 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc av cc v ss ? 0.3 v ss + 4.0 v *2 avr v ss ? 0.3 v ss + 4.0 *2 input voltage* 1 v i1 v ss ? 0.3 v ss + 4.0 v other than p80 to p83* 3 v i2 v ss ? 0.3 v ss + 6.0 p80 to p83 output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 4 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 4 ?l? level maximum output current i ol1 ? 15 ma other than p00 to p07 i ol2 15 p00 to p07 ?l? level average current i olav1 ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i olav2 12 p00 to p07 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p00 to p07 i oh2 ? 15 p00 to p07 ?h? level average current i ohav1 ? ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 p00 to p07 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins) mb95100b series 32 (continued) *1 : the parameter is based on av ss = v ss = 0.0 v. *2 : apply equal potential to av cc and v cc . avr should not exceed av cc + 0.3 v. *3 : v i1 and vo should not exceed v cc + 0.3 v. v i1 must not exceed the rating voltage. however, if the maximum current to/from an input is limited by so me means with external components, the i clamp rating supersedes the v i1 rating. *4 : applicable to pins : p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71, pe0 to pe3, pg0 ? use within recommended operating conditions. ? use at dc voltage (current). ? the + b signal is an input signal that exceeds v cc voltage. the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistanc e should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated va lues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is lo w, such as in the power saving modes, the +b input potential may pass through the protective diode and increase th e potential at the v cc pin, and this affects other devices. ? note that if the + b signal is inputted when the microcontroller powe r supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature t stg ? 55 + 150 c mb95107b, mb95f108bs, mb95f108bw ? 40 + 125 mb95r107b, mb95d108bs, mb95d108bw p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode mb95100b series 33 2. recommended operating conditions (av ss = v ss = 0.0 v) * : the values vary with the operating frequency. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter sym- bol pin name condition value unit remarks min max power supply voltage v cc , av cc ?? 1.8* 3.3 v at normal operating, flash memory product, t a = ? 10 c to + 85 c ?? 1.8* 3.6 at normal operating, mask rom product, t a = ? 10 c to + 85 c ?? 2.0* 3.3 at normal operating, flash memory product, t a = ? 40 c to + 85 c ?? 2.0* 3.6 at normal operating, mask rom product, t a = ? 40 c to + 85 c ?? 2.7 3.3 at normal operating, flash memory product, at fram access, t a = ? 40 c to + 85 c ?? 2.7 3.6 at normal operating, mask rom product, at fram access, t a = ? 40 c to + 85 c ?? 2.6 3.6 mb95fv100d-101 t a = + 5 c to + 35 c ?? 1.5 3.3 retain status in stop mode, flash memory product ?? 1.5 3.6 retain status in stop mode, mask rom product a/d converter reference input voltage avr ?? 1.8 av cc v operating temperature t a ?? ? 40 + 85 c mb95100b series 34 3. dc characteristics (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?h? level input voltage v ih1 p10, p67 *1 0.7 v cc ? v cc + 0.3 v at selecting cmos input level v ih2 p50, p51 ? 0.7 v cc ? v ss + 5.5 v at selecting cmos input level mb95f108bs, mb95f108bw, mb95107b, mb95fv100d-101 ? v cc + 0.3 at selecting cmos input level mb95d108bs, mb95d108bw, mb95r107b v ihs1 p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p60 to p67, p70, p71, pe0 to pe3, pg0, pg1* 2 , pg2* 2 *1 0.8 v cc ? v cc + 0.3 v hysteresis input v ihs2 p80 to p83 *1 0.8 v cc ? v ss + 5.5 v hysteresis input v ihs3 p50, p51 ? 0.8 v cc ? v ss + 5.5 v hysteresis input mb95f108bs, mb95f108bw, mb95107b, mb95fv100d-101 ? v ss + 5.0 hysteresis input mb95d108bs, mb95d108bw, mb95r107b v ihm rst , mod ? 0.7 v cc ? v cc + 0.3 v cmos input (flash memory product) ? 0.8 v cc ? v cc + 0.3 v hysteresis input (mask rom product) mb95100b series 35 (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?l? level input voltage v il p10, p50, p51, p67 *1 v ss ? 0.3 ? 0.3 v cc v at selecting cmos input level (hysteresis input) v ils p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p80 to p83, pe0 to pe3, pg0, pg1* 2 , pg2* 2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm rst , mod ? v ss ? 0.3 ? 0.3 v cc v cmos input (flash memory product) ? v ss ? 0.3 ? 0.2 v cc v hysteresis input (mask rom product) input leakage current (hi-z output leakage current) i li port other than p50, p51, p80 to p83 0.0 v < v i < v cc ? 5 ? + 5 a when the pull-up is prohibition setting ?h? level output voltage v oh1 output pin other than p00 to p07 i oh = ? 4.0 ma 2.4 ?? v v oh2 p00 to p07 i oh = ? 8.0 ma 2.4 ?? v ?l? level output voltage v ol1 output pin other than p00 to p07 i ol = 4.0 ma ?? 0.4 v v ol2 p00 to p07 i ol = 12 ma ?? 0.4 v open-drain output application voltage v d1 p80 to p83 ? v ss ? 0.3 ? v ss + 5.5 v v d2 p50, p51 ? v ss ? 0.3 ? v ss + 5.5 mb95f108bs, mb95f108bw, mb95107b v cc + 0.3 mb95d108bs, mb95d108bw, mb95r107b open-drain output leakage current i liod p50, p51, p80 to p83 0.0 v < v i < v ss + 5.5 v ?? 5 a mb95100b series 36 (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max pull-up resistor r pull p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71, pe0 to pe3, pg0, pg1* 2 , pg2* 2 v i = 0.0 v 25 50 100 k ? when the pull-up is permission setting pull-down resistor r mod mod v i = v cc 25 50 100 k ? mask rom product input capacitance c in other than av cc , av ss , avr, v cc , v ss f = 1 mhz ? 515pf power supply current* 3 i cc v cc (external clock operation) f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 11.0 14.0 ma mb95f108bs, mb95f108bw (at other than flash memory writing and erasing) ? 30.0 35.0 ma mb95f108bs, mb95f108bw (at flash memory writing and erasing) ? 7.3 10.0 ma mb95107b f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ? 17.6 22.4 ma mb95f108bs, mb95f108bw (at other than flash memory writing and erasing) ? 38.1 44.9 ma mb95f108bs, mb95f108bw (at flash memory writing and erasing) ? 11.7 16.0 ma mb95107b f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) when fram read and write (f scl = 400 khz) ? 11.1 15.0 ma mb95d108bs, mb95d108bw (at other than flash memory writing and erasing) ? 30 35 ma mb95d108bs, mb95d108bw (at flash memory write and erase) ? 7.4 11.0 ma mb95r107b mb95100b series 37 (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 3 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) when fram read and write (f scl = 400 khz) ? 17.7 22.5 ma mb95d108bs, mb95d108bw (at other than flash memory writing and erasing) ? 38.1 44.9 ma mb95d108bs, mb95d108bw (at flash memory write and erase) ? 11.8 16.1 ma mb95r107b i ccs f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 6.0 ma f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 7.2 9.6 ma i ccl f cl = 32 khz f mpl = 16 khz sub clock mode (divided by 2) , t a = + 25 c ? 25 35 a i ccls f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) , t a = + 25 c ? 715 a i cct f cl = 32 khz watch mode main stop mode t a = + 25 c ? 210 a flash memory product ? 15 a mask rom product i ccmpll f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 10 14 ma flash memory product ? 6.7 10.0 ma mask rom product f ch = 6.4 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) ? 16.0 22.4 ma flash memory product ? 10.8 16.0 ma mask rom product mb95100b series 38 (continued) (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : p10, p50, p51, and p67 can switch the input level to either the ?cmos input level? or ?hysteresis input level?. the switching of the input level can be set by the input level selection register (ilsr). *2 : single clock product only *3 : power supply current is regulated by external clock. ? refer to ?4. ac characteristics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 3 i ccspll v cc (external clock operation) f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 190 250 a i cts f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.4 0.5 ma i cch sub stop mode t a = + 25 c ? 15 a i a av cc f ch = 10 mhz at operating of a/d conversion ? 1.3 2.2 ma i ah f ch = 10 mhz at stopping of a/d conversion t a = + 25 c ? 15 a mb95100b series 39 4. ac characteristics (1) clock timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name conditions value unit remarks min typ max clock frequency f ch x0, x1 ? 1.00 ? 16.25 mhz when using main oscillation circuit 1.00 ? 32.50 mhz when using external clock 3.00 ? 10.00 mhz main pll multiplied by 1 3.00 ? 8.13 mhz main pll multiplied by 2 3.00 ? 6.50 mhz main pll multiplied by 2.5 3.00 ? 4.06 mhz main pll multiplied by 4 f cl x0a, x1a ? 32.768 ? khz when using sub oscillation circuit ? 32.768 ? khz when using sub pll flash memory product : v cc = 2.3 v to 3.3 v mask rom product : v cc = 2.3 v to 3.6 v clock cycle time t hcyl x0, x1 61.5 ? 1000 ns when using main oscillation circuit 30.8 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub oscillation circuit, when using external clock input clock pulse width t wh1 t wl1 x0 61.5 ?? ns when using external clock, duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 10 ns when using external clock mb95100b series 40 t hcyl t wh1 t cr 0.2 v cc x0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 ? input wave form for using external clock (main clock) x0 x1 f ch x0 f ch x1 microcontroller microcontroller c1 c2 ? figure of main clock i nput port external connection when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.1 v cc x0a 0.8 v cc 0.8 v cc 0.1 v cc 0.1 v cc t cf t wl2 ? input wave form for using external clock (sub clock) x0a x1a f cl x0a f cl x1a microcontroller microcontroller c1 c2 ? figure of sub clock input port external connection when using a crystal or ceramic oscillator when using external clock open mb95100b series 41 (2) source clock/machine clock (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock di vision ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machin e clock division ratio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the source clock can be selected as follow. ? main clock divided by 2 ? pll multiplication of main clock (selec t from 1, 2, 2.5, 4 multiplication) ? sub clock divided by 2 ? pll multiplication of sub clock (select from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follow. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol pin name value unit remarks min typ max source clock cycle time* 1 (clock before setting division) t sclk ? 61.5 ? 2000 ns when using main clock min : f ch = 8.125 mhz, pll multiplied by 2 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using sub clock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when using main clock f spl ? 16.384 ? 131.072 khz when using sub clock machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 100 ? 32000 ns when using main clock min : f sp = 16.25 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using sub clock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.250 mhz when using main clock f mpl 1.024 ? 131.072 khz when using sub clock mb95100b series 42 f ch (m a in o s cill a tion) f cl ( sub o s cill a tion) divided b y 2 m a in pll 1 2 2.5 4 divided b y 2 sub pll 2 3 4 s clk ( s o u rce clock) clock mode s elect b it ( s ycc: s c s 1, s c s 0) mclk (m a chine clock) divi s ion circ u it 1 1/4 1/ 8 1/16 ? outline of clock generation block mb95100b series 43 ? operating voltage - operating frequency (when t a = ? 10 c to + 85 c) mb95107b, mb95r107b mb95f108bs, mb95f108bw, mb95d108bs, mb95d108bw 131.072 khz 16.384 khz 1.8 3.6 2.3 32 khz 16.25 mhz 0.5 mhz 3 .6 1. 8 5 mhz 3 mhz 2.7 sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode pll operation source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range fram operating guarantee range main clock mode and main pll mode operation guarantee range 131.072 khz 16.384 khz 1.8 3.3 2.3 32 khz 16.25 mhz 0.5 mhz 3 . 3 1. 8 7.5 mhz 3 mhz 2.7 sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range fram operating guarantee range main clock mode and main pll mode operation guarantee range mb95100b series 44 ? operating voltage - op erating frequency (when t a = ? 40 c to + 85 c) mb95107b, mb95r107b mb95f108bs, mb95f108bw, mb95d108bs, mb95d108bw 131.072 khz 16.384 khz 1.8 3.6 2.3 32 khz 16.25 mhz 0.5 mhz 3 .6 1. 8 5 mhz 3 mhz 2.7 sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range fram operating guarantee range main clock mode and main pll mode operation guarantee range 131.072 khz 16.384 khz 2.0 3.3 2.3 32 khz 16.25 mhz 0.5 mhz 3 . 3 2.0 5 mhz 3 mhz 2.7 sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range fram operating guarantee range main clock mode and main pll mode operation guarantee range mb95100b series 45 ? operating voltage - operating frequency (t a = + 5 c to + 35 c) mb95fv100d-101 131.072 khz 16.384 khz 2.6 3.6 32 khz 10 mhz 0.5 mhz 3 .6 2.6 3 . 3 16.25 mhz 3 mhz source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range fram, main clock mode and main pll mode operation guarantee range mb95100b series 46 [mhz] 16.25 16 15 12 10 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8 .125 10 [mhz] ? main pll operation frequency machine clock frequency (f mp ) source clock frequency (fsp) 2.5 2 1 4 mb95100b series 47 (3) external reset (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation start time of oscillator is the time that the amplitude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillato rs, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 2 t mclk * 1 ? ns at stop mode, sub clock mode, sub sleep mode, and watch mode t r s tl 0.2 v cc r s t 0.2 v cc t r s tl 0.2 v cc 0.2 v cc 2 t mclk r s t x0 ? at normal operating ? at stop mode, sub clock mode, su b sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction mb95100b series 48 (4) power-on reset (av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) note : the power supply must be turned on wi thin the selected oscillation stabilization time. note : sudden change of power supply voltage may activate the power-on reset function. when changing power supply voltages during operation, set the slope of rising with in 20 mv/ms as shown below. parameter symbol conditions value unit remarks min max power supply rising time t r ?? 36 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 1.5 v 0.2 v v cc v cc 1.5 v v ss hold c ondition in stop mode limiting the slope of rising within 20 mv/ms is recommended. mb95100b series 49 (5) peripheral input timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil mb95100b series 50 (6) uart/sio, serial i/o timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc uck0 internal clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 0 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t iv s h 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc t s hix t s lov 0. 8 v 2.4 v 0. 8 v 2.4 v uck0 uo0 ui0 0. 8 v t s cyc t iv s h t s hix t s lov 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc 2.4 v uck0 uo0 ui0 0. 8 v 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t s l s h t s h s l internal shift clock mode external shift clock mode mb95100b series 51 (7) lin-uart timing sampling at the rising edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performe d at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns mb95100b series 52 0. 8 v0. 8 v 2.4 v t s lovi t iv s hi t s hixi 2.4 v 0. 8 v s ck s ot s in t s cyc 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc t s love t iv s he t s hixe 2.4 v 0. 8 v t r t f s ck s ot s in t s l s h t s h s l 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc 0. 8 v cc 0.2 v cc 0.2 v cc internal shift clock mode external shift clock mode mb95100b series 53 sampling at the falling edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns mb95100b series 54 0. 8 v 2.4 v 2.4 v t s hovi t iv s li t s lixi 2.4 v 0. 8 v s ck s ot s in t s cyc 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc t s hove t iv s le t s lixe 2.4 v 0. 8 v t f t r s ck s ot s in t s h s l t s l s h 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc internal shift clock mode external shift clock mode mb95100b series 55 sampling at the rising edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 0. 8 v 0. 8 v t s hovi 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 2.4 v 0. 8 v t s cyc t s ovli t iv s li t s lixi mb95100b series 56 sampling at the falling edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 2.4 v 0. 8 v t s lovi 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 2.4 v 0. 8 v t s cyc t s ovhi t iv s hi t s hixi mb95100b series 57 (8) i 2 c timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hd;dat have only to be met if the devi ce dose not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. parameter symbol pin name conditions value unit standard-mode fast-mode min max min max scl clock frequency f scl scl0 r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta scl0 sda0 4.0 ? 0.6 ? s scl clock ?l? width t low scl0 4.7 ? 1.3 ? s scl clock ?h? width t high scl0 4.0 ? 0.6 ? s (repeat) start condition set- up time scl sda t su;sta scl0 sda0 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl0 sda0 03.45* 2 00.9* 3 s data setup time sda scl t su;dat scl0 sda0 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl0 sda0 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl0 sda0 4.7 ? 1.3 ? s s da0 s cl0 t wakeup t hd; s ta t s u;dat t hd; s ta t s u; s ta t low t hd;dat t high t s u; s to t buf mb95100b series 58 (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condi- tions value* 2 unit remarks min max scl clock ?l? width t low scl0 r = 1.7 k ? , c = 50 pf* 1 (2 + nm / 2) t mclk ? 20 ? ns master mode scl clock ?h? width t high scl0 (nm / 2) t mclk ? 20 (nm / 2 ) t mclk + 20 ns master mode start condition hold time t hd;sta scl0 sda0 ( ? 1 + nm / 2) t mclk ? 20 ( ? 1 + nm) t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode start condition setup time t su;sta scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl0 sda0 (2 nm + 4) t mclk ? 20 ? ns data hold time t hd;dat scl0 sda0 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl0 sda0 ( ? 2 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl0 (nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl0 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl0 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception mb95100b series 59 (continued) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and lo ad capacitor of the scl and sda lines. *2 : ? refer to ? (2) source clock/machine clock? for t mclk . ? m is cs4 bit and cs3 bit (bit 4 and bit 3) of clock control register (iccr) . ? n is cs2 bit to cs0 bit (bit 2 to bit 0) of clock control register (iccr) . ? actual timing of i 2 c is determined by m and n values set by the machine clock (t mclk ) and cs4 to cs0 of iccr0 register. ? standard-mode : m and n can be set at t he range : 0.9 mhz < t mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 10 mhz ? fast-mode : m and n can be set at t he range : 3.3 mhz < t mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter sym- bol pin name condi- tions value* 2 unit remarks min max stop condition detection t su;sto scl0 sda0 r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception restart condition detection condition t su;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception bus free time t buf scl0 sda0 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl0 sda0 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl0 sda0 t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl0 sda0 0 ? ns at reception data setup time t su;dat scl0 sda0 t mclk ? 20 ? ns at reception sda scl (at wakeup function) t wakeup scl0 sda0 oscillation stabilization wait time + 2 t mclk ? 20 ? ns mb95100b series 60 5. a/d converter (1) a/d converter electrical characteristics (av cc = v cc = 1.8 v to 3.3 v [flash memory product], av cc = v cc = 1.8 v to 3.6 v [mask rom product], av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v flash memory product : 2.7 v av cc 3.3 v mask rom product : 2.7 v av cc 3.6 v av ss ? 0.5 lsb av ss + 1.5 lsb av ss + 3.5 lsb v 1.8 v av cc < 2.7 v full-scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v flash memory product : 2.7 v av cc 3.3 v mask rom product : 2.7 v av cc 3.6 v avr ? 2.5 lsb avr ? 0.5 lsb avr + 1.5 lsb v 1.8 v av cc < 2.7 v compare time ? 1.3 ? 140 s flash memory product : 2.7 v av cc 3.3 v mask rom product : 2.7 v av cc 3.6 v 20 ? 140 s 1.8 v av cc < 2.7 v sampling time ? 0.4 ?? s flash memory product : 2.7 v av cc 3.3 v mask rom product : 2.7 v av cc 3.6 v ex- ternal impedance < at 1.8 k ? 30 ?? s 1.8 v av cc < 2.7 v external impedance < at 14.8 k ? analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain av ss ? avr v reference voltage ? av ss + 1.8 ? av cc v avr pin reference voltage supply current i r ? 400 600 a avr pin, during a/d operation i rh ?? 5 a avr pin, at stop mode mb95100b series 61 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exter nal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/ d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suff icient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avr ? av ss | becomes smaller, values of relative errors grow larger. r c analog input pin note : the values are reference values. ? analog input equivalent circuit rc 2.7 v av cc 3.6 v 1.7 k ? (max) 14.5 pf (max) 1.8 v av cc < 2.7 v 84 k ? (max) 25.2 pf (max) comparator during sampling : on 0 5 10 15 20 25 30 35 40 0 10 20 30 40 50 60 70 80 90 100 01234 0 2 4 6 8 10 12 14 16 18 20 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] av cc 1.8 v av cc 2.7 v av cc 2.7 v ? the relationship between external impedance and minimum sampling time mb95100b series 62 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straig ht line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device a nd the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss avr av ss v nt avr {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = avr ? av ss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : a voltage at which digital output transits from (n - 1) to n. = mb95100b series 63 (continued) v (n + 1) t ? v nt 1 lsb av ss avr av ss avr av ss avr v nt av ss avr 001 h 002 h 00 3 h 004 h 3 fc h 3 fd h 3 fe h 3 ff h 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h n - 2 h n - 1 h n h n + 1 h { 1 l s b n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst (measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n linear error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst (measurement value) v ot (measurement value) n : a/d converter digital output value v nt : a voltage at which digital outp ut transits from (n - 1) to n. v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] ideal characteristics = = mb95100b series 64 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 3.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 2.7 v, 10000 cycles *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . 7. fram program characteristics * : number of data read/write parameter value unit remarks min typ max sector erase time (4k bytes sector) ? 0.2* 1 3.0* 2 s excludes 00 h programming prior erasure. sector erase time (16k bytes sector) ? 0.5* 1 12.0* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3600 s excludes system-level overhead. program/erase cycle 10000 ?? cycle power supply voltage at program/erase 2.7 ? 3.3 v flash memory data retention time 20* 3 ?? year average t a = + 85 c parameter value unit remarks min typ max read/write cycle* 10 10 ?? cycle power supply voltage at read/write 2.7 ? 3.6 v data retention time 10 ?? year t a = 0 c to + 55 c mb95100b series 65 mask option *1 : refer to table below about cl ock mode select and load of fram. *2 : low voltage detection reset and clock supervisor are options of 5-v products. no. part number mb95107b mb95r107b mb95f108bs mb95d108bs mb95f108bw mb95d108bw mb95fv100d-101 specifying procedure specify when ordering mask setting disabled setting disabled setting disabled 1 clock mode select* 1 ? single-system clock mode ? dual-system clock mode selectable single-system clock mode dual-system clock mode changing by the switch on mcu board 2 fram* 1 ? with load of fram ? without load of fram specify by part number specify by part number specify by part number no 3 low voltage detection reset* 2 ? with low voltage detection reset ? without low voltage detection reset no no no no 4 clock supervisor* 2 ? with clock supervisor ? without clock supervisor no no no no 5 selection of oscillation stabilization wait time ? selectable the initial value of main clock oscillation stabilization wait time selectable 1 : (2 2 ? 2) /f ch 2 : (2 12 ? 2) /f ch 3 : (2 13 ? 2) /f ch 4 : (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch part number clock mode select load of fram mb95107b/r107b single-system no dual-system no mb95f108bs single-system no mb95d108bs yes mb95f108bw dual-system no mb95d108bw yes mb95fv100d-101 single-system no dual-system no mb95100b series 66 ordering information part number package MB95107BPFV mb95f108bspfv mb95f108bwpfv mb95r107bpfv mb95d108bspfv mb95d108bwpfv 64-pin plastic lqfp (fpt-64p-m03) mb95107bpfm mb95f108bspfm mb95f108bwpfm mb95r107bpfm mb95d108bspfm mb95d108bwpfm 64-pin plastic lqfp (fpt-64p-m09) mb2146-301a (mb95fv100d-101pbt) mcu board () 224-pin plastic pfbga (bga-224p-m08) mb95100b series 67 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m0 3 ) (fpt-64p-m0 3 ) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 0 ? ~ 8 ? "a" 0.0 8 (.00 3 ) (.006.002) 0.1450.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) 12.000.20(.472.00 8 ) s q 10.000.10(. 3 94.004) s q index 49 64 33 4 8 17 3 2 16 1 200 3 fujit s u limited f64009 s -c-5- 8 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. mb95100b series 68 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12 12 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m09) (fpt-64p-m09) c 200 3 fujit s u limited f6401 8s -c- 3 -5 0.65(.026) 0.10(.004) 116 17 3 2 49 64 33 4 8 12.000.10(.472.004) s q 14.000.20(.551.00 8 ) s q index 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) 0.1450.055 (.0057.0022) "a" .059 ?.004 +.00 8 ?0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) 0.10(.004) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. mb95100b series f0612 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept. |
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